[OpenSIPS-Devel] [OpenSIPS/opensips] 498dd2: - mips inline asm gcc 3.x warnings fixed

[Liviu Chircu]

  Branch: refs/heads/master
  Home:   https://github.com/OpenSIPS/opensips
  Commit: 498dd2af8896393924d4095dddec4775aec4786b
      https://github.com/OpenSIPS/opensips/commit/498dd2af8896393924d4095dddec4775aec4786b
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  - mips inline asm gcc 3.x warnings fixed
- mips2 NOSMP mode (skip sync)
- minor x86 & mips optimizations


  Commit: c84bee61a130b25c797da84c0b12438deb1ef690
      https://github.com/OpenSIPS/opensips/commit/c84bee61a130b25c797da84c0b12438deb1ef690
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  - support for mips cpu which don't implement full mips isa2, but do support
 ll and sc


  Commit: 722fd2bd6a72a43c84cbfb8f36cfa588c7215037
      https://github.com/OpenSIPS/opensips/commit/722fd2bd6a72a43c84cbfb8f36cfa588c7215037
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  - fastlock: minor fixes


  Commit: 7ad38e5cb148d8e1ecda612510dfcd189920b6d7
      https://github.com/OpenSIPS/opensips/commit/7ad38e5cb148d8e1ecda612510dfcd189920b6d7
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  - x86/x86_64 lock optimizations:  spinning on a lock should be friendlier now
  for the other cpus caches (at the extra cost of a cmp mem + jump) ; tried to
  arrange a little better the instructions to allow for some parallel
  execution.

- x86 unlocks with xchg by default (since some x86s reorder stores, so a
 simple mov is unsafe)


  Commit: 6871464c47a52e67f319dfa19aff3fa916aa4a33
      https://github.com/OpenSIPS/opensips/commit/6871464c47a52e67f319dfa19aff3fa916aa4a33
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  - ppc fixes (s/stw/stwx/, s/lwz/lwzx)
- missing early clobbers added for x86, sparc*, armv6, ppc*, alpha


  Commit: d986daa83bce55801b0d39e0fcbad5bb1b8f1531
      https://github.com/OpenSIPS/opensips/commit/d986daa83bce55801b0d39e0fcbad5bb1b8f1531
  Author: Maksym Sobolyev <sobomax at sippysoft.com>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  Small arm optimization from the d3da8467113.


  Commit: 30329f67b9603df45973f4608841ac8d4384e65f
      https://github.com/OpenSIPS/opensips/commit/30329f67b9603df45973f4608841ac8d4384e65f
  Author: Andrei Pelinescu-Onciul <andrei at iptel.org>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h
    A sched_yield.h

  Log Message:
  -----------
  - moved sched_yield() wrapper into sched_yield.h at Miklos's request.


  Commit: 6924b5b5dbb3f1c6d26ade2d1509e1dd18b49c70
      https://github.com/OpenSIPS/opensips/commit/6924b5b5dbb3f1c6d26ade2d1509e1dd18b49c70
  Author: Maksym Sobolyev <sobomax at sippysoft.com>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M fastlock.h

  Log Message:
  -----------
  Reduce diff to a83e261254. Merge few more ARM/Sparc fixes from the
d3da8467113.


  Commit: 323896a65be5b5775f89d374668c1fc3c0b92cda
      https://github.com/OpenSIPS/opensips/commit/323896a65be5b5775f89d374668c1fc3c0b92cda
  Author: Maksym Sobolyev <sobomax at sippysoft.com>
  Date:   2020-11-19 (Thu, 19 Nov 2020)

  Changed paths:
    M .travis.yml

  Log Message:
  -----------
  Add MIPS64 cross-build.


  Commit: 7790bf929147dedd13edcb58e3ab3e9269c8ba0e
      https://github.com/OpenSIPS/opensips/commit/7790bf929147dedd13edcb58e3ab3e9269c8ba0e
  Author: Liviu Chircu <liviu at opensips.org>
  Date:   2020-11-25 (Wed, 25 Nov 2020)

  Changed paths:
    M .travis.yml
    M fastlock.h
    A sched_yield.h

  Log Message:
  -----------
  Merge pull request #2301 from sippy/pr_fastlock_merge

Fix MIPS64, add MIPS64 cross-build for travis, merge updates into fastlocks.h


Compare: https://github.com/OpenSIPS/opensips/compare/85a484eabf58...7790bf929147